A conventional image processing device has a structure as illustrated in FIG. 2. It complexes a CPU 1 and an image data memory 2 which are connected to each other by way of an address bus 3 and a data bus 4.
The CPU 1 supplies address data to the image data memory 2 by way of the address bus 3, and reads the image data from and writes the image data in the image data memory 2 (hereinafter referred to "access") by way of the data bus 4. As a result, an image data is generated. In case of accessing a target image data, it must be accessed in the image data memory 2 every time the CPU 1 operates the image data. That is, the CPU1 has to repeat the operation of reading the image data from the image data memory 2 to subject the image data to operation and thereafter writing the image data in the image data memory 2 as many times as the number of the image data.
For example, suppose that a letter "V" is subjected to operation for writing the same on a letter "A" in an example of writing image data as illustrated in FIG. 3. If both of the letters "A" and "V" are composed of the data of 32 bits.times.32 words (1 word having 32 bits) and the CPU 1 has the bandwidth of 32 bits, drawing the letters "A" and "V" requires 32 times of reading operation and 32 times of writing operation respectively. Consequently, 128 times of accessing the image data memory 2 are required in total. Therefore, it takes much time in image processing (hereinafter referred to access time).
There is an image processing device designed to expedite the image processing for reducing the frequency of accessing the image data memory 2 as illustrated in FIG. 4.
The image processing device comprises a CPU 11, an image data memory 12 and a cache storage 13 which is provided between the former two. Furthermore, the CPU 11 and the cache storage 13 are coupled to each other by way of an address bus 14 and a data bus 15, while the image data memory 12 and the cache storage 13 are coupled to each other by way of an address bus 16 and a data bus 17. The image data memory 12 is composed of a plurality of block areas B0 to B9, while the cache storage 13 is composed of a plurality of entry areas E0 to E4. A technique relating to the cache storage is disclosed in pp.31 to 42 in "High Quality Computer Architecture" authored by Tadao Saito and Hiroshi Hatta, published by Maruzen Co. Ltd.
The CPU 11 supplies address data to the cache storage 13 by way of the address bus 14 and receives image data from the cache storage 13 and supplies the same thereto by way of the data bus 15. Moreover, the cache storage 13 supplies the address data to the image data memory 12 by way of the address bus 16 and receives the image data therefrom and supplies the same thereto by way of the data bus 17.
An operation of the thus constructed image processing device in accessing the image data will be described hereinafter.
If there is no image data required by the CPU 11 in the cache storage 13, the cache storage 13 reads out the image data from the data memory 12 and supplies the read image to the CPU 11. For example, the cache storage 13 caches the target image data of the letter "A" which is stored in blocks B3 to B6 of the image data memory 12 in the entry areas E1 to E4 of the cache storage 13 as illustrated in FIG. 4. If the cache storage 13 has the necessary image data therein, accessing the image data is performed only between the CPU 11 and the cache storage 13.
Furthermore, the cache storage 13 renews the image data in the image data memory 12 in a batch when the image data in the image data memory 12 need to be renewed so that the CPU 11 does not directly take part in it. Accordingly, the image data in the image data memory 12 can be renewed by reading the same therefrom and writing the same therein only once even if the image data are accessed a plurality of times.
In this way, the image data processing device has an advantage of processing the image at high speed since the CPU 11 accesses only the cache storage 13 which can be accessed faster compared with the image data memory 12.
In this image data processing device, however, the cache storage 13 accesses not only the target image data, but also unnecessary data in the same entry area together with it since it accesses by the entry area. As a result, there is a problem that it takes much access time due to unnecessary access.
Furthermore, there is another problem that the presence of the unnecessary data in the cache storage 13 reduces the hit rate of the requested data cached therein (the probability of finding the requested data in the cache storage 13) so that the access efficiency is reduced.
Therefore, a measure for erasing the unnecessary areas can be considered by dividing the entry areas of the cache storage 13 into smaller ones in order to eliminate the unnecessary areas, however, it is not a sufficient measure since the memories for storing the tags of the entry areas therein (i.e., indexes for each entry area address) are increased, so that the components of the device as a whole are increased in number.
It is the object of the present invention to provide an image processing device solving such problems of the prior art set forth above that it takes much access time and the access efficiency is reduced.